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G339S - 74LS175D SMD IC Quad D Flip-Flop
The LSTTL/MSI 74LS175D is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175D is fabricated with the Schottky barrier diode process for high speed.
Features:
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
SOIC 16 package. Actual brand may vary from picture.
G339S
Features:
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
SOIC 16 package. Actual brand may vary from picture.
G339S
$0.15
Original: $0.42
-64%G339S - 74LS175D SMD IC Quad D Flip-Flop—
$0.42
$0.15Product Information
Product Information
Shipping & Returns
Shipping & Returns
Description
The LSTTL/MSI 74LS175D is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175D is fabricated with the Schottky barrier diode process for high speed.
Features:
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
SOIC 16 package. Actual brand may vary from picture.
G339S
Features:
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
SOIC 16 package. Actual brand may vary from picture.
G339S
